//////////// CLOCK ////////// input CLOCK_50,
`include "fixedpt.vh"
module GPU(
//////////// CLOCK ////////// input CLOCK_50,
//////////// SDRAM ////////// // output [12:0] DRAM_ADDR, // output [1:0] DRAM_BA, // output DRAM_CAS_N, // output DRAM_CKE, // output DRAM_CLK, // output DRAM_CS_N, // inout [15:0] DRAM_DQ, // output DRAM_LDQM, // output DRAM_RAS_N, // output DRAM_UDQM, // output DRAM_WE_N,
//////////// SEG7 ////////// output [6:0] HEX0, output [6:0] HEX1, // output [6:0] HEX2, // output [6:0] HEX3, // output [6:0] HEX4, // output [6:0] HEX5,
//////////// KEY ////////// input [3:0] KEY,
//////////// LED ////////// output [9:0] LEDR,
//////////// SW ////////// // input [9:0] SW,
//////////// VGA ////////// output [7:0] VGA_B, output VGA_BLANK_N, output VGA_CLK, output [7:0] VGA_G, output VGA_HS, output [7:0] VGA_R, output VGA_SYNC_N, output VGA_VS ); wire clk25, clk4;
CLKDivider clkdiv(.clk(CLOCK_50), .clkdiv2(clk25), .clkdiv16(clk4));
//=======================================================
reg `FIXPT x1 = `FIXPT_INT(10'd10); reg `FIXPT y1 = `FIXPT_INT(10'd10); reg `FIXPT x2 = `FIXPT_INT(10'd50); reg `FIXPT y2 = `FIXPT_INT(10'd200); reg `FIXPT x3 = `FIXPT_INT(10'd300); reg `FIXPT y3 = `FIXPT_INT(10'd140);
reg [7:0] r1 = 255; reg [7:0] r2 = 120; reg [7:0] r3 = 30;
reg [7:0] g1 = 100; reg [7:0] g2 = 255; reg [7:0] g3 = 22;
reg [7:0] b1 = 24; reg [7:0] b2 = 100; reg [7:0] b3 = 255;
wire write_pixel;
wire [15:0] vram_address_x; wire [15:0] vram_address_y;
wire [17:0] raster_address = (vram_address_y*320) + vram_address_x;
wire [7:0] r8; wire [7:0] g8; wire [7:0] b8;
wire [15:0] raster_color = ((b8 >> 3) & 5'h1F) | (((g8 >> 2) & 6'h3f) << 5) | (((r8 >> 3) & 5'h1f) << 11);
wire draw_enable = ~KEY[0]; reg enable_vertex_color =0;
always @(negedge KEY[2]) begin enable_vertex_color <= !enable_vertex_color; end
TriRasterEngine tre( .i_clk (CLOCK_50), .i_reset (~KEY[3]), .i_draw (draw_enable), .i_v1_x (x1), .i_v1_y (y1), .i_v1_r (enable_vertex_color ? r1 : 0), .i_v1_g (enable_vertex_color ? g1 : 0), .i_v1_b (enable_vertex_color ? b1 : 0), .i_v1_u (9'd0), .i_v1_v (9'd0),
.i_v2_x (x2), .i_v2_y (y2), .i_v2_r (enable_vertex_color ? r2 : 0), .i_v2_g (enable_vertex_color ? g2 : 0), .i_v2_b (enable_vertex_color ? b2 : 0), .i_v2_u (9'd0), .i_v2_v (9'd127),
.i_v3_x (x3), .i_v3_y (y3), .i_v3_r (enable_vertex_color ? r3 : 0), .i_v3_g (enable_vertex_color ? g3 : 0), .i_v3_b (enable_vertex_color ? b3 : 0), .i_v3_u (9'd127), .i_v3_v (9'd127),
.o_color_r (r8), .o_color_g (g8), .o_color_b (b8), .o_x (vram_address_x), .o_y (vram_address_y), .o_write_pixel (write_pixel), .o_busy (LEDR[0]), .o_done (LEDR[1]) );
//=======================================================
wire [4:0] rng; wire [4:0] rng2; reg [4:0] rv1 = 0; reg [4:0] rv2 = 0; reg [4:0] rv3 = 0; reg [4:0] rv4 = 0; lfsr_5bit #(5'h1F) xrng( .i_clk (CLOCK_50), .i_reset (KEY[3]), .o_data (rng) ); lfsr_5bit #(5'h11) xrng2( .i_clk (CLOCK_50), .i_reset (KEY[3]), .o_data (rng2) );
always @(posedge CLOCK_50) begin rv1 <= rng; rv2 <= rng2; rv3 <= rv2; rv4 <= rv1+rv2;
x1 <= `FIXPT_INT(rv1 * 8); x2 <= `FIXPT_INT(rv2 * 8 + 1); x3 <= `FIXPT_INT(rv3 * 8 + 2); y1 <= `FIXPT_INT(rv4 * 8 + 3); y2 <= `FIXPT_INT(rv3 * 8 + 4); y3 <= `FIXPT_INT(rv1 * 8 + 5);
r1 <= r1 + rv1; r2 <= r2 - rv2; r3 <= r3 + rv4;
g1 <= g1 - rv3; g2 <= g2 + rv1; g3 <= g3 + rv4;
b1 <= b1 + rv1; b2 <= b2 + rv4; b3 <= b3 - rv3;
end
assign HEX0 = raster_address; assign HEX1 = write_pixel;
wire [15:0] fb_vram_address; wire [15:0] fb_pixel;
VRAM vram( // framebuffer .i_a_clk (clk25), .i_a_address (fb_vram_address), .i_a_write_enable (1'b0), .i_a_wr_data (16'b0), .o_a_rd_data (fb_pixel),
// gpu .i_b_clk (CLOCK_50), .i_b_address (raster_address), .i_b_write_enable (write_pixel), .i_b_wr_data (raster_color) );
VGAFramebuffer vga_fb( .i_clk (clk25), .i_pixel (fb_pixel), .o_address (fb_vram_address), .o_vga_clk (VGA_CLK), .o_vga_r (VGA_R), .o_vga_g (VGA_G), .o_vga_b (VGA_B), .o_vga_blank_n (VGA_BLANK_N), .o_vga_sync_n (VGA_SYNC_N), .o_vga_hs (VGA_HS), .o_vga_vs (VGA_VS) );
endmodule